In a typical non-volatile flash EEPROM (or EAROM) a memory array is usually erased by erasing an entire block of memory cells. The memory cells are organized along a number of word lines and a number of bit lines. The memory array contains data denoted as `1` and `0`, which values are determined by the threshold voltage of the particular cell in question. As is well known, the threshold voltage of the cell, in turn, is determined by the amount of charge stored on the floating gate, which charge therefore dictates the state of the core cell. Accordingly, the data in the core transistor of the flash EEPROM cell is read as a `1` if the core transistor is at an `on` state, and such data is similarly read as a `0` if the core transistor is at an `off` state.
A core transistor in the non-volatile flash EEPROM is considered at its `on` state if the transistor conducts more core cell current than a reference core cell transistor, whereas the core transistor is considered at its `off` state if it conducts less core cell current than the reference core cell transistor. The amount of current conducted by the core transistor is a direct function of the amount of charge stored on the floating gate, and this in turn affects the turn-on voltage. A number of different operations during normal use of a flash memory cell will affect the charge on the floating gate, and for this reason a substantial amount of effort is made to ensure that such operations effectuate the proper response from such cell (i.e., that a predictable and proper amount of charge remains on such gate after such operation).
One of these typical steps in the use of a flash cell array is an "erase" operation. The purpose of this step is to remove charge from the floating gates, and thus place them into a "1" data state condition. It is very critical to control the threshold voltage distribution in the non-volatile flash EEPROM after each erase operation, since the memory array may be "over" erased; this means that the core cell transistor exhibits a negative threshold voltage. It is apparent that if the flash memory array experiences over-erasure, erroneous data may be retrieved from the memory array. Furthermore, it is even conceivable that the entire non-volatile flash memory may be no longer operated reliably if the floating gate of the cell has so deteriorated that it can no longer acquire meaningul differences in charge so that the difference between an `on` state and an `off` state can be detected. This can be true if the cell is extremely leaky, i.e., in the sense that it cannot hold charge. In other cases it is possible that it will render a substantial amount of other cells unusable because it will conduct so much current that it will swamp the "on" current of adjoining cells and make them essentially irrelevant.
Correction of over-erased cells in a non-volatile flash EEPROM, therefore, is a far more critical operation than most because over-erased cells not only cause erratic operation on the said flash memory array, they also greatly reduce the number of times the core array may be re-programmed. Preventing the occurence of over-erased cells in a non-volatile flash memory is therefore extremely desirable; as a corrolary to this, of course, it is apparent that excessive use of embedded erase algorithms should be avoided whenever possible.
To prevent over-erasure, prior art systems have employed a mechanism as shown generally in FIG. 1B. Instead of applying a single "erase" pulse, which might drive a large number of the voltage thresholds of the lower group of cells into an over-erase condition, a first "program" operation is instead effectuated on the entire array. This has the effect of moving all the threshold voltages into the area generally bounded by Vt.sub.pmin and Vt.sub.pmax. Then, a second "erase" operation has the effect of placing the threshold voltages of the cells into the area bounded by Vt.sub.emin and Vt.sub.emax. This procedure is not perfect, however, and a significant number of cells can still end up being over-erased as shown by the dotted line portion of FIG. 1B. These cells, in turn, must be identified, and, if any are found to exist, an erase correction pulse is applied to rectify the threshold voltages. In any event, it is apparent that the above methodology is non-optimal since it requires that the array be first programmed before an erase procedure can occur, and this stressing cycle exacts a toll on the lifespan of a part incorporating such array.